As central compute clusters integrate multiple SoCs (e.g. NVIDIA Thor, Qualcomm Ride, and safety microcontrollers) inside a single aluminum enclosure, architects must choose the inter-SoC communication fabric. While Ethernet offers robust fault isolation and cable reach, PCIe switches deliver sub-microsecond zero-copy direct memory access.
PCIe Non-Transparent Bridging (NTB) enables an autonomous driving SoC to write directly into an infotainment display SoC's frame buffer in under 120 nanoseconds with zero software interrupt overhead. By contrast, transporting that buffer over 10G Ethernet requires packetizing, socket context switching, and checksum validation, pushing total latency to 45 microseconds.
PCIe signals degrade rapidly over copper traces, practically limiting transmission distances to less than 40 centimeters without expensive re-timers, making PCIe unsuitable for connecting distant zonal gateways across the vehicle chassis. Furthermore, an uncontained PCIe bus hang (e.g. fatal Malformed TLP) can crash the host root complex, whereas Ethernet switches isolate physical faults completely.